In an effort to move next-generation computing systems forward, Task 6.2 deals with the M³ (Modular, Multicore, and Managed) Platform, designed to enable secure and efficient system-on-chip (SoC) designs. In a recent interview, Michael Roitzsch, project coordinator at Barkhausen Institute, shared the recent progress and insights from the lab demo.
The M³ platform is a tile-based SoC design where each tile, whether a processor, an accelerator, or a memory controller, is protected by a Trusted Communication Unit (TCU). This allows each tile to execute independently and efficiently while the TCU addresses system-level security and isolation. According to Michael, this has been effective in integrating untrusted third-party IP blocks without compromising system integrity. “The TCUs do the isolation, so the tiles can do whatever they want. The isolation portion is separated from what’s on the tiles,” he said.
Measured Performance with Minimal Trade-offs
Prototypes of the M³ platform have been evaluated on FPGA and custom chip implementations. The results have shown minimal impact on most workloads on performance. “There is a bit of latency introduced by communication checks, but it doesn’t play a large role in energy efficiency or throughput,” Roitzsch noted. The approach offers robust security without compromising the high performance of the components.
Handling Cache Coherency and Future Enhancements
A key challenge to creating M³ has been figuring out how to implement security without sacrificing computational efficiency. By extending the burden of isolation out to the TCUs, the platform isn’t forced to introduce a security obligation directly into each of the processing units. Roitzsch said an area that requires further development is cache coherency, which isn’t presently supported. “It’s a feature that’s useful for certain workloads, and we’d like to do it in a trustworthiness-aware fashion—so even cache traffic is controlled by the TCU,” he said.
As COREnext continues its progress, the M³ platform is still set to demonstrate the potential of secure, modular, and scalable SoC design—a foundation for disaggregated and composable computing systems of the future in Europe and beyond.